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| DATA SHEET 128MB Direct Rambus DRAM RIMM Module EBR12UC8ABFD (64M words x 16 bits) Description The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and low latency are required. The EBR12UC8ABFD consists of 4 pieces of 288M Direct Rambus DRAM (Direct RDRAM) devices. These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits 1066MHz or 800MHz transfer rates while using conventional system and board design technologies. The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous, randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM device's 32 banks support up to four simultaneous transactions per device. Features * 128MB Direct RDRAM storage and 128 banks total on module * High speed 1066MHz/800MHz Direct RDRAM devices * 184 edge connector pads with 1mm pad spacing Module PCB size: 133.35mm x 34.925mm x 1.27mm Gold plated edge connector pads contacts * Serial Presence Detect (SPD) support * Operates from a 2.5V supply * Low power and power down self refresh modes * Separate Row and Column buses for higher efficiency * RDRAM devices use Chip Scale Package (CSP) FBGA package EO Document No. E0319E21 (Ver. 2.1) Date Published March 2006 (K) Japan URL: http://www.elpida.com L This product became EOL in April, 2004. Elpida Memory, Inc. 2002-2006 Pr od uc t EBR12UC8ABFD Ordering Information Part number EBR12UC8ABFD-AEP EBR12UC8ABFD-AE EBR12UC8ABFD-AD EBR12UC8ABFD-8C 800 Organization 64M x 16 I/O Freq. (MHz) 1066 RAS access time (ns) Package 32 (32P) 32 35 40 184 edge connector pads RIMM with heat spreader Edge connector: Gold plated Mounted devices EDR2518ABSE Module Pad Names Pad A1 Signal Name GND Pad B1 B2 B3 B4 B5 B6 B7 B8 B9 Signal Name GND LDQA7 GND LDQA5 GND LDQA3 GND LDQA1 GND LCFM GND LCFMN GND Pad A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 Signal Name NC NC NC NC VREF GND SCL VDD SDA SVDD SWP VDD RSCK GND RDQB7 GND RDQB5 GND RDQB3 Pad B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 Signal Name NC NC NC NC VREF GND SA0 VDD SA1 SVDD SA2 VDD RCMD GND RDQB8 GND RDQB6 GND RDQB4 GND RDQB2 GND RDQB0 GND RCOL1 EO A2 A3 LDQA8 GND A4 LDQA6 GND A5 A6 LDQA4 GND A7 A8 LDQA2 GND A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 LDQA0 GND LCTMN GND LCTM GND NC GND LROW1 GND LCOL4 GND LCOL2 GND LCOL0 GND LDQB1 GND LDQB3 GND LDQB5 GND LDQB7 GND LSCK Data Sheet E0319E21 (Ver. 2.1) L B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 Pr NC A60 GND A61 LROW2 GND A62 A63 LROW0 GND LCOL3 GND LCOL1 GND LDQB0 GND LDQB2 GND LDQB4 GND LDQB6 GND LDQB8 GND LCMD A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 od GND RDQB1 GND RCOL0 GND RCOL2 GND RCOL4 GND RROW1 GND NC GND RCTM GND B66 B67 B68 B69 B70 B71 uc B72 GND B73 RCOL3 B74 GND B75 RROW0 B76 GND B77 RROW2 t GND NC GND B78 B79 B80 2 EBR12UC8ABFD Pad A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 Signal Name VCMOS SOUT VCMOS NC GND NC VDD VDD NC NC NC Pad B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 Signal Name VCMOS SIN VCMOS NC GND NC VDD VDD NC NC NC NC Pad A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 Signal Name RCTMN GND RDQA0 GND RDQA2 GND RDQA4 GND RDQA6 GND RDQA8 GND Pad B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 Signal Name RCFMN GND RCFM GND RDQA1 GND RDQA3 GND RDQA5 GND RDQA7 GND EO NC Data Sheet E0319E21 (Ver. 2.1) L Pr od uc t 3 EBR12UC8ABFD Module Connector Pad Description Signal Module Connector Pads A1, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29, A31, A33, A39, A52, A60, A62, A64, A66, A68, A70, A72, A74, A76, A78, A80, A82, A84, A86, A88, A90, A92, B1, B3, B5, B7, B9, B11, B13, B15, B17, B19, B21, B23, B25, B27, B29, B31, B33, B39, B52, B60, B62, B64, B66, B68, B70, B72, B74, B76, B78, B80, B82, B84, B86, B88, B90, B92 B10 B12 I/O Type Description GND -- -- Ground reference for RDRAM core and interface. 72 PCB connector pads. EO LCFM LCFMN LCMD B34 LCOL4..LCOL0 LCTM LCTMN LDQA8..LDQA0 LDQB8..LDQB0 LROW2..LROW0 LSCK A14 A12 A34 NC RCFM RCFMN RCMD RCOL4..RCOL0 RCTM RCTMN RDQA8..RDQA0 RDQB8..RDQB0 B83 B81 B59 A79 A81 Data Sheet E0319E21 (Ver. 2.1) I I I I I I RSL RSL VCMOS RSL RSL RSL RSL RSL A20, B20, A22, B22, A24 A2, B2,A4, B4, A6, B6, A8, I/O B8, A10 B32, A32, B30, A30, B28, I/O A28, B26, A26, B24 B16, A18, B18 I RSL I VCMOS Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. Row bus. 3-bit bus containing control and address information for row accesses. Serial clock input. Clock source used to read from and write to the RDRAM control registers. These pads are not connected. These 24 connector pads are reserved for future use. RROW2..RROW0 B77, A75, B75 L A73, B73, A71, B71, A69 A16, B14, A38, B38, A40, B40, A77, B79, A43, B43, A44, B44, A45, B45, A46, B46, A47, B47, A48, B48, A49, B49, A50, B50 A91, B91, A89, B89, A87, B87, A85, B85, A83 B61, A61, B63, A63, B65, A65, B67, A67, B69 Pr -- -- I I I I I I I/O I/O I RSL RSL VCMOS RSL RSL RSL RSL RSL RSL od 4 Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command Input used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. Row bus. 3-bit bus containing control and address information for row accesses. uc t EBR12UC8ABFD Signal RSCK SA0 SA1 SA2 SCL SDA SIN Module Connector Pads A59 B53 B55 B57 A53 A55 B36 I/O I I I I I I/O I/O Type VCMOS SVDD SVDD SVDD SVDD SVDD VCMOS Description Serial clock input. Clock source used to read from and write to the RDRAM control registers. Serial Presence Detect Address 0. Serial Presence Detect Address 1. Serial Presence Detect Address 2. Serial Presence Detect Clock. Serial Presence Detect Data (Open Collector I/O). Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of the first RDRAM on the module. Serial I/O for reading from and writing to the control registers. Attaches to SIO1 of the last RDRAM on the module. SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2. Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. Supply voltage for the RDRAM core and interface logic. Logic threshold reference voltage for RSL signals. SOUT A36 I/O -- I -- -- -- VCMOS -- SVDD -- -- -- EO SVDD SWP A57 VCMOS VDD VREF Data Sheet E0319E21 (Ver. 2.1) A56, B56 A35, B35, A37, B37 A41, A42, A54, A58, B41, B42, B54, B58 A51, B51 L Pr od uc t 5 EBR12UC8ABFD VDD VCMOS LDQA 8 LDQA 7 LDQA 6 LDQA 5 LDQA 4 LDQA 3 LDQA 2 LDQA 1 LDQA 0 LCFM LCFMN LCTM LCTMN LROW 2 LROW 1 LROW 0 LCOL 4 LCOL 3 LCOL 2 LCOL 1 LCOL 0 LDQB 0 LDQB 1 LDQB 2 LDQB 3 LDQB 4 LDQB 5 LDQB 6 LDQB 7 LDQB 8 DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 Data Sheet E0319E21 (Ver. 2.1) SIN LSCK LCMD VREF EO Block Diagram L SIO 0 SIO 1 SIO 0 SIO 1 SIO 0 SIO 1 CMD CMD VREF SCK VREF SCK Pr U2 U3 SIO 0 CMD VREF SCK DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 od U4 SIO 1 CMD VREF SCK SOUT RSCK RCMD RDQA 8 RDQA 7 RDQA 6 RDQA 5 RDQA 4 RDQA 3 RDQA 2 RDQA 1 RDQA 0 RCFM RCFMN RCTM RCTMN RROW 2 RROW 1 RROW 0 RCOL 4 RCOL 3 RCOL 2 RCOL 1 RCOL 0 RDQB 0 RDQB 1 RDQB 2 RDQB 3 RDQB 4 RDQB 5 RDQB 6 RDQB 7 RDQB 8 Note: 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain. 2. See Serial Presence Detection Specification for information on the SPD device and its contents. U1 uc SVDD t VCC SCL SDA WP U0 A0 A1 A2 SDA Serial PD SWP SCL SA0 SA1 SA2 6 EBR12UC8ABFD Electrical Specifications Absolute Maximum Ratings Symbol VI,ABS VDD,ABS TSTORE Parameter Voltage applied to any RSL or CMOS signal pad with respect to GND Voltage on VDD with respect to GND Storage temperature min. -0.3 -0.5 -50 max. VDD + 0.3 VDD + 1.0 +100 Unit V V C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. EO Symbol VDD VCMOS VREF SVDD Data Sheet E0319E21 (Ver. 2.1) DC Recommended Electrical Conditions Parameter and conditions Supply voltage* 1 min. 2.50 - 0.13 2.50 - 0.13 1.8 - 0.1 1.4 - 0.2 max. 2.50 + 0.13 2.50 + 0.25 1.8 + 0.2 1.4 + 0.2 3.6 Unit V V V V V CMOS I/O power supply at pad 2.5V controllers 1.8V controllers 1 Note: See Direct RDRAM datasheet for more details. L Reference voltage* Serial Presence Detector- positive power 2.2 supply Pr od uc t 7 EBR12UC8ABFD AC Electrical Specifications Symbol Z Parameter and Conditions Module Impedance of RSL signals Module Impedance of SCK and CMD signals TPD TPD TPD-CMOS TPD- SCK,CMD Average clock delay from finger to finger of all RSL clock nets (CTM, CTMN,CFM, and CFMN) Propagation delay variation of RSL signals with respect 1, 2 to TPD * Propagation delay variation of SCK signal with respect 1 to an average clock delay * Propagation delay variation of CMD signal with respect to SCK signal Attenuation Limit -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C Grade min. 25.2 23.8 -- -21 -250 -200 typ. 28.0 28.0 -- -- -- -- max. 30.8 32.2 1.56 21 250 200 Unit ns ps ps ps EO V/VIN VXF/VIN VXB/VIN RDC Symbol TPD -- -- 17.0 % Forward crosstalk coefficient (300ps input rise time 20% - 80%) -- -- 4.0 % Backward crosstalk coefficient (300ps input rise time 20% - 80%) -- -- 2.0 % Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN). 2. If the RIMM module meets the following specification, then it is compliant to the specification. If the RIMM module does not meet these specifications, then the specification can be adjusted by the "Adjusted TPD Specification" table. Adjusted TPD Specification Parameter and conditions Propagation delay variation of RSL signals with respect to TPD L DC Resistance Limit -- -- 0.8 Pr 8 Absolute min. -30 max. 30 Unit ps Adjusted min./max. od +/- [17+(18*N*Z0)] * 1 Note: 1 N = Number of RDRAM devices installed on the RIMM module. Z0 = delta Z0% = (max. Z0 - min. Z0) / (min. Z0) (max. Z0 and min. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the module.) uc t Data Sheet E0319E21 (Ver. 2.1) EBR12UC8ABFD RIMM Module Current Profile IDD IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 RIMM module power conditions * One RDRAM device in Read * , balance in NAP mode 2 One RDRAM device in Read * , balance in Standby mode 2 One RDRAM device in Read * , balance in Active mode One RDRAM device in Write, balance in NAP mode One RDRAM device in Write, balance in Standby mode One RDRAM device in Write, balance in Active mode 2 1 Grade -AEP, -AE, -AD -8C -AEP, -AE, -AD -8C -AEP, -AE, -AD -8C -AEP, -AE, -AD -8C -AEP, -AE, -AD -8C -AEP, -AE, -AD -8C max. 672 532 930 730 1050 820 692 542 950 740 1070 830 Unit mA mA mA mA mA mA EO Data Sheet E0319E21 (Ver. 2.1) Notes: 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage patterns. Power does not include Refresh Current. 2. I/O current is a function of the % of 1's, to add I/O power for 50 % 1's for a x18 need to add 276mA for the following: VDD = 2.5V, VTERM = 1.8V, VREF = 1.4V and VDIL = VREF - 0.5V. L Pr od uc t 9 EBR12UC8ABFD Physical Outline Unit: mm 4.00 0.10 R2.00 Pad A1 5.68 45.00 55.175 A 32.0 11.50 133.35 45.00 66.675 17.78 34.925 1.270.10 4.46 Max Pad A92 3.00 0.10 2.99 0.30 0.10 EO Data Sheet E0319E21 (Ver. 2.1) Note: The dimensions without tolerance specification use the default tolerance of 0.13. L detail of A part 0.80 R1.00 Pr 2.000.10 1.00 od 10 ECA-TS2-0079-01 uc t EBR12UC8ABFD CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES EO 1 2 3 Data Sheet E0319E21 (Ver. 2.1) PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. L Pr 11 od uc CME0107 t EBR12UC8ABFD Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc. Direct Rambus, Direct RDRAM, RIMM, SO-RIMM and QRSL are trademarks of Rambus Inc. The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. EO Data Sheet E0319E21 (Ver. 2.1) L Pr 12 od M01E0107 uc t |
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